1. Field of the Invention
The present invention relates to a method of estimating the power consumption of a semiconductor integrated circuit, and particularly, to one that estimates the power consumption according to the signal and switching probabilities of each logic circuit incorporated in the integrated circuit.
2. Description of the Prior Art
A semiconductor integrated circuit such as a CMOS integrated circuit consumes power largely when the capacitance of each net of wires contained in the circuit is charged or discharged. The power consumption of a net N in the circuit is estimated as follows: EQU PWR(N)=1/2VDD.sup.2 .multidot.CN.multidot.f.multidot.PSWT(N)(1)
where PWR(N) is the power consumption of the net N, VDD is a source voltage, CN is the capacitance of the net N, f is a clock frequency, and PSWT(N) is the switching probability of the net N.
The switching probability of the net N is the probability of the net N of changing its logical value from 0 to 1, or from 1 to 0. The signal probability of the net N is the probability of the net N of providing 1 and is represented with PSIG(N).
VDD and f in the expression (1) are known, and CN is calculable. Accordingly, the power consumption PWR(N) is calculable if the switching probability PSWT(N) is obtained.
The switching probability of a given circuit can be estimated by simulation or by calculation.
The simulation is made by applying pattern data, i.e., test vectors to primary input terminals of the circuit and by measuring the number of switching times of the output of each net contained in the circuit.
The accuracy of the simulation will improve if the test vectors are extended. This, however, elongates a testing time.
On the other hand, the probability calculation employs no test vectors. This technique provides the signal and switching probabilities of primary inputs to a circuit and calculates the propagation of the probabilities to internal nets of the circuit. The probability calculation completes in a short time because it employs no test vectors. The accuracy thereof, however, is relatively low.
The probability calculation has been developed mainly in the field of combinational circuits but not in the field of sequential circuits because the sequential circuits involve peculiar difficulties. These difficulties and a prior art to cope with them will be explained.
FIG. 7 shows a sequential circuit 9 consisting of a combinational logic part 5 and a latch group 7. All latches in the latch group 7 are edge trigger latches that transfer an input to an output terminal only when a clock signal changes from 0 to 1, and in the other cases, keep the output terminal unchanged. Accordingly, the latch group 7 serves as a delay element whose delay time is equal to a clock period, i.e., a unit time.
The logic part 5 is made of logic elements such as NANDs and ORs. The delay of each logic element is ignored. The logic part 5 receives external inputs from an external circuit as well as internal inputs, which are outputs of the latch group 7. Outputs of the logic part 5 are internal inputs to the latch group 7.
The external inputs are dependent on primary inputs. Logical values of the internal inputs determine the state of the sequential circuit 9. The primary inputs are independent of one another and have each temporal autocorrelation.
In FIG. 7, a set of the primary inputs is expressed as X={X1 to Xn}, a set of the external inputs as A={A1 to Am}, and a set of the internal inputs as S={S1 to S1}.
Symbols used for probabilities will be explained.
The probability of a logical function f of providing a logical value of 1 is P(f), which has temporal translation invariance. If the logical function f is dependent on time t1 to tp, the following is true for any number: EQU P(f(t1, . . . , tp))=P(f(t1+t, . . . , tp+t)) (2)
Then, the signal and switching probabilities of a net N are expressed as follows: EQU PSIG(N)=P(N), (3) EQU PSWT(N)=P(N(1)N(0))+P(N(1)N(0)) (4)
where N(t) is a logical value provided by the net N at time t. This expression does not positively show temporal dependency because of the temporal translation invariance of the probability.
It is known that the following is identically true: EQU P(N(1)N(0))=P(N(1)N(0))
Accordingly, the switching probability of the net N is expressed as follows: ##EQU1##
Independence of logical functions will be defined.
Logical functions f and g are independent of each other if logical functions F(f) and G(g) that are dependent only on f and g, respectively, are as follows: EQU P(F(f)G(g))=P(F(f))P(G(g)) (6)
Namely, if the logical functions f and g are independent of each other, the following stands: EQU P(fg)=P(f)P(g) (7) EQU P(f(t1)g(t1)f(t2)g(t2)) =P(f(t1)f(t2))P(g(t1)g(t2)) (8)
where f(t) and g(t) are logical values at time t.
Next, the difficulties in calculating the signal and switching probabilities of a sequential circuit will be explained.
Generally, the probability of an output from a gate is calculated on an assumption that the probability of each input to the gate is known. In the sequential circuit 9 of FIG. 7, the logical values of the internal inputs are equal to the one-clock-behind logical values of the internal outputs, and the logical values of the internal outputs are logical functions of the concurrent logical values of the internal inputs. Namely, the logical values of the internal inputs are dependent on the one-clock-behind logical values of themselves. This is expressed as follows: EQU S(t)=F(S(t-1), A(t-1)) (9)
where F is a Boolean vector function determined by the structure of the logic part 5, and S and A are Boolean vectors defined as follows: ##EQU2## where Sk(t) (k=1 to 1) and Ai(t) (i=1 to m) are logical values at time t. As is apparent in the expression (9), there is contradiction that the probability of an internal input to a sequential circuit is calculable if itself is known. This is a dilemma in calculating the signal and switching probabilities of a sequential circuit.
A prior art to cope with the dilemma will be explained.
The expression (9) is recurrent with respect to S, and S(k) is expressible with A(0) to A(k-1) and S(0). For example, S(2) is expressed with A(0), A(1), and S(0) as follows: EQU S(2)=F(F(S(0), A(0)), A(1)) (12)
Recurrently using the expression (9) is equivalent to unrolling the sequential circuit in question. FIG. 8 shows the sequential circuit of FIG. 7 unrolled k times where k is an unroll number. Unrolling a sequential circuit is equal to converting the same into a combinational circuit. The unroll number k is determined according to correlation among the internal inputs. This technique handles S(0) as an additional primary input, to approximate the correlation among the signals. Increasing the unroll number k will increase accuracy of the approximation.
The signal probability of the unrolled circuit is expressed as follows: EQU P(S(k))=P(S(0)) (13)
A probability P(S(t)) at time t is a vector having real numbers as follows: ##EQU3##
The expression (13) considers S(k) as a function of A(0) to A(k-1) and S(0).
The expression (13) can be approximated according to Picard-Peano method or Newton-Raphson method. The Picard-Peano method will be explained.
1. Step 1 sets any value, for example, 0.5 for P(S(0)) and sets f=0.
2. Step 2 calculates the signal probability P(S(k)) of the output S(k) of the unrolled circuit.
3. Step 3 substitutes the calculated probability P(S(k)) for P(S(0)).
4. Step 4 increments f by one. If f&lt;fmax, then step 2 is carried out, and if not, the method ends.
This method is an unroll feedback method. The value fmax used in step 4 is a feedback number. Accuracy of the calculated signal probability and calculation time of this method are dependent on the probability calculation carried out in step 2.
If the probability calculation is improper, an error will be enlarged whenever the feedback operation is carried out. Since the unrolled circuit is a combinational circuit, the probability calculation may be made according to a conventional method suitable for the combinational circuit.
The unrolled circuit most consider temporal correlation among the external inputs A(0) to A(k-1). In this regard, the prior art mentioned above is incapable of providing an accurate result because it is based on a delay-zero model that never considers the temporal correlation among external inputs. It is necessary to provide a probability calculation method that considers temporal correlation among external inputs in estimating the power consumption of a sequential circuit.
In "Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs" in Proceedings of the 31st Design Automation Conference, pp. 18-23, 1994, C. Y. Tsui, M. Pedram, and A. M. Despain have disclosed a probability calculation method that forms a binary decision diagram (BDD) for covering the whole of an unrolled circuit, to realize utmost accuracy. Calculation time of this method exponentially increases with respect to the product of an unroll number and the number of external inputs. Accordingly, this method is inapplicable to a large-scale sequential circuit.
To reduce calculation time, it is necessary to form a binary decision diagram not for the whole of an unrolled circuit and to directly calculate the probability of the output of each logic part according to the probabilities of inputs thereto. This is called an incremental method. A simplest form of the incremental method ignores correlation. This is called a completely uncorrelated model. This model approximates the switching probability of a net N as follows: EQU PSWT(N).apprxeq.2P(N) P(N) (15)
This model approximates the signal probability of an output Z of a 2-input AND gate as follows: EQU P(Z).apprxeq.P(A) P(B) (16)
where A and B are inputs to the 2-input AND gate. Calculation time of the completely uncorrelated model is proportional only to the scale of an unrolled circuit, and therefore, is shortest among all probability calculation models. Its calculation error, however, is very large and reaches even 100% because it completely ignores correlation among signals.
As explained above, the conventional methods are incapable of accurately estimating the switching probability, i.e., power consumption of a large-scale sequential circuit.